freescale semiconductor advance d clock drivers device data 513 freescale semiconductor, inc. technical data order number: mpc962308 rev 3, 08/2004 3.3 v zero delay buffer the mpc962308 is a 3.3 v zero delay buffer designed to distribute high-speed clocks in pc, workstati on, datacom, telecom and other high-performance applications. the mpc9 62308 uses an internal pll and an external feedback path to lock its low-skew clock output phase to the reference clock phase, providing virtually zero propagation delay. the input-to-output skew is guaranteed to be less than 250 ps and output-to-output skew is guaranteed to be less than 200 ps. features ? 1:8 outputs lvcmos zero-delay buffer ? zero input-output propagation delay, adjustable by the capacitive load on fbk input ? multiple configurations, see table 11. available mpc962308 configurations ? multiple low-skew outputs ? 200 ps max output-output skew ? 700 ps max device-device skew ? two banks of four outputs, output tr istate control by two select inputs ? supports a clock i/o frequency range of 10 mhz to 133 mhz ? low jitter, 200 ps max cycle-cycle (-1, -1h, -4, -5h) ? 250 ps static phase offset (spo) ? 16-pin soic package or 16-pin tssop package ? single 3.3 v supply ? ambient temperature range: ?40 c to +85 c ? compatible with the cy2308 and cy23s08 ? spread spectrum compatible functional description the mpc962308 has two banks of four outputs each which c an be controlled by the select inputs as shown in table 10. select input decoding . bank b can be tristated if all of the outputs are not required. the select inputs also allow the input clock to be directly applied to the output for chip and system te sting purposes. the mp c962308 pll enters a power down st ate when there are no risin g edges on the ref input. during this state, all of th e outputs are in tristate and there is less than 50 a of current draw. the pll shuts down in two additional cases explained in table 10. select input decoding . multiple mpc962308 devices can accept and distribute the same i nput clock throughout the system. in this situation, the differe nce between the output skews of two devices will be less than 700 ps. the mpc962308 is available in five different configurations as shown in table 11. available mpc962308 configurations . in the mpc962308-1, the reference frequency is reproduced by the pll and pr ovided at the outputs. a high drive version of this configu ra- tion, the mpc962308-1h, is available to provide faster rise and fall times of the device. the mpc962308-2 provides 2x and 1x the reference frequency at the output banks. in addition, the mpc962308-3 provides 4x and 2x the reference frequency at the output banks. the output banks driving the f eedback will determine the different configur ations of the above devices. the mpc962308-4 prov ides outputs 2x the reference frequency .the mpc962308-5h is a high drive version with outputs of ref/2. the mpc962308 is fully 3.3 v compatible and requires no extern al components for the internal pll. all inputs accept lvcmos signals while the outputs provide lvcmos compatible levels with the capability to drive terminated 50 ? transmission lines on the incident edge. depending on the configuration, the devi ce is offered in a 16-lead soic or 16-lead tssop package. mpc962308 dt suffix 16-lead tssop package case 948f-01 d suffix 16-lead soic package case 751b-05
mpc962308 514 freescale semiconductor advanc ed clock drivers device data table 10. select input decoding s2 s1 clock a1?a4 clock b1?b4 o utput source pll shutdown 0 0 three-state three-state pll y 0 1 driven three-state pll n 10 driven 1 1. outputs inverted on mpc962308-2 in bypass mode, s2=1 and s1=0. driven 1 reference y 1 1 driven driven pll n table 11. available mpc962308 configurations device feedback from bank a frequency bank b frequency mpc962308-1 bank a or bank b reference reference mpc962308-1h bank a or bank b reference reference mpc962308-2 bank a reference reference/2 mpc962308-2 bank b 2 x reference reference mpc962308-3 bank a 2 x reference reference or reference [1] 1. output phase is indeterminate (0 or 180 from input clock). if phase integr ity is required, use the mpc962308-2. mpc962308-3 bank b 4 x reference 2 x reference mpc962308-4 bank a or bank b 2 x reference 2 x reference mpc962308-5h bank a or bank b reference /2 reference /2 soic/tssop top view pin configuration clka1 clka2 clka3 clka4 clkb1 clkb2 clkb3 clkb4 fbk pll mux /2 select input decoding /2 /2 s2 s1 ref extra divider (-3, -4) extra divider (-5h) extra divider (-2, -3) block diagram 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 fbk clka4 clka3 v dd gnd clkb4 clkb3 s1 ref clka1 clka2 v dd gnd clkb1 clkb2 s2
mpc962308 freescale semiconductor advance d clock drivers device data 515 table 12. pin description pin signal description 1 ref 1 1. weak pull-down. input reference frequency, 5 v tolerant input 2 clka1 2 2. weak pull-down on all outputs. clock output, bank a 3 clka2 2 clock output, bank a 4v dd 3.3 v supply 5 gnd ground 6 clkb1 2 clock output, bank b 7 clkb2 2 clock output, bank b 8 s2 3 3. weak pull-ups on these inputs. select input, bit 2 9 s1 3 select input, bit 1 10 clkb3 2 clock output, bank b 11 clkb4 2 clock output, bank b 12 gnd ground 13 v dd 3.3 v supply 14 clka3 2 clock output, bank a 15 clka4 2 clock output, bank a 16 fbk pll feedback input table 13. maximum ratings characteristics value unit supply voltage to ground potential ?0.5 to +3.9 v dc input voltage (except ref) ?0.5 to v dd +0.5 v dc input voltage ref ?0.5 to 5.5 v storage temperature ?65 to +150 c junction 150 c static discharge voltage (per mil-std-883, method 3015) >2000 v
mpc962308 516 freescale semiconductor advanc ed clock drivers device data table 14. operating conditions for mpc 962308-x industrial temperature devices parameter description min max unit v dd supply voltage 3.0 3.6 v t a operating temperature (ambient temperature) ?40 85 c c l load capacitance, below 100 mhz 30 pf load capacitance, from 100 mhz to 133 mhz 15 pf c in input capacitance 1 1. applies to both ref clock and fbk. 7pf table 15. electrical charact eristics for mpc962308-x indu strial temperature devices 1 1. all parameters are s pecified with loaded outputs. parameter description test conditions min max unit v il input low voltage 0.8 v v ih input high voltage 2.0 v i il input low current v in = 0v 50.0 a i ih input high current v in = v dd 100.0 a v ol output low voltage 2 2. parameter is guaranteed by design and characterization. not 100% tested in production. i ol = 8 ma (-1, -2, -3, -4) i ol = 12 ma (-1h, -5h) 0.4 v v oh output high voltage 2 i oh = -8 ma (-1, -2, -3, -4) i oh = -12 ma (-1h, -5h) 2.4 v i dd (pd mode) power down supply current ref = 0 mhz 25.0 a i dd supply current unloaded outputs, 100 mhz, select inputs at v dd or gnd 45.0 ma 70(-1h, -5h) ma unloaded outputs, 66-mhz ref (-1, -2, -3, -4) 35.0 ma unloaded outputs, 35-mhz ref (-1, -2, -3, -4) 20.0 ma
mpc962308 freescale semiconductor advance d clock drivers device data 517 table 16. switching characteristics for mp c962308-x industrial temperature devices 1 1. all parameters are s pecified with loaded outputs. parameter name test conditions min typ max unit t 1 output frequency 30-pf load, all devices 10 100 mhz t 1 output frequency 2 2. parameter is guaranteed by design and characterization. not 100% tested in production. 20-pf load, -1h, -5h devices 10 133.3 mhz t 1 output frequency 2 15-pf load, -1, -2, -3, -4 devices 10 133.3 mhz duty cycle 2 = t 2 t 1 (-1, -2, -3, -4, -1h, -5h) measured at 1.4 v, fout =66.66 mhz 30-pf load 40.0 60.0 % duty cycle 2 = t 2 t 1 (-1, -2, -3, -4, -1h, -5h) measured at 1.4 v, fout <50.0 mhz 15-pf load 45.0 55.0 % t 3 rise time 2 (-1, -2, -3, -4) measured between 0.8 v and 2.0 v, 30-pf load 2.50 ns rise time 2 (-1, -2, -3, -4) measured between 0.8 v and 2.0 v, 15-pf load 1.50 ns rise time 2 (-1h, -5h) measured between 0.8 v and 2.0 v, 30-pf load 1.50 ns t 4 fall time 2 (-1, -2, -3, -4) measured between 0.8 v and 2.0 v, 30-pf load 2.50 ns fall time 2 (-1, -2, -3, -4) measured between 0.8 v and 2.0 v, 15-pf load 1.50 ns fall time 2 (-1h, -5h) measured between 0.8 v and 2.0 v, 30-pf load 1.25 ns output-to-output skew on same bank (-1, -2, -3, -4) 2 all outputs equally loaded 200 ps t 5 output-to-output skew (-1h, -5h) all outputs equally loaded 200 ps output bank a to output bank b skew (-1, -4, -5h) all outputs equally loaded 200 ps output bank a to output bank b skew (-2, -3) all outputs equally loaded 400 ps t 6 delay, ref rising edge to fbk rising edge 2 measured at v dd /2 0 250 ps t 7 device-to-device skew 2 measured at v dd /2 on the fbk pins of devices 0 700 ps t 8 output slew rate 2 measured between 0.8 v and 2.0 v on -1h, -5h device using test circuit # 2 1 v/ns t j cycle-to-cycle jitter (-1, -1h, -4, -5h) 2 measured at 66.67 mhz, loaded outputs, 15-pf load 200 ps measured at 66.67 mhz, loaded outputs, 30-pf load 200 ps measured at 133.3 mhz, loaded outputs, 15 pf load 100 ps t j cycle-to-cycle jitter (-2, -3) 2 measured at 66.67 mhz, loaded outputs 30-pf load 400 ps measured at 66.67 mhz, loaded outputs 15-pf load 400 ps t lock pll lock time 2 stable power supply, valid clocks presented on ref and fbk pins 1.0 ms
mpc962308 518 freescale semiconductor advanc ed clock drivers device data applications information figure 1. outpu t-to-output skew t sk(o) figure 2. static phase offset test reference figure 3. output duty cycle (dc) v cc v cc 2 gnd v cc v cc 2 gnd t 6 cclk fb_in the pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device v cc 1.4 v gnd v cc 1.4 v gnd t 5 the time from the pll controlled edge to the non-controlled edge, divided by the time between pll controlled edges, expressed as a percentage v cc 1.4 v gnd t 2 t 1 dc = t 2 /t 1 x 100% figure 5. cycle-to-cycle jitter t 4 t 3 v cc = 3.3 v 2.0 0.8 figure 6. output transition time test reference the variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs t n t j = | t n ?t n+1 | t n+1 figure 4. device-to-device skew v cc v cc 2 gnd v cc v cc 2 gnd t 7 device 1 device 2
mpc962308 freescale semiconductor advance d clock drivers device data 519 ordering information (available) ordering code package name package type mpc962308d-1 d16 16-pin 150-mil soic mpc962308d-1r2 d16 16-pin 150-mil soic ? tape and reel mpc962308d-1h d16 16-pin 150-mil soic mpc962308d-1hr2 d16 16-pin 150-mil soic ? tape and reel mpc962308dt-1h dt16 16-pin 150-mil tssop mpc962308dt-1hr2 dt16 16-pin 150-mil tssop ? tape and reel mpc962308d-2 d16 16-pin 150-mil soic mpc962308d-2r2 d16 16-pin 150-mil soic ? tape and reel ordering information (planned) ordering code package name package type mpc962308d-3 d16 16-pin 150-mil soic mpc962308d-3r2 d16 16-pin 150-mil soic ? tape and reel mpc962308d-4 d16 16-pin 150-mil soic mpc962308d-4r2 d16 16-pin 150-mil soic ? tape and reel mpc962308d-5h d16 16-pin 150-mil soic mpc962308d-5hr2 d16 16-pin 150-mil soic ? tape and reel mpc962308dt-5h dt16 16-pin 150-mil tssop mpc962308dt-5hr2 dt16 16-pin 150-mil tssop ? tape and reel 0.1 f 0.1 f clk out c load v dd v dd outputs gnd gnd test circuit #1 test circuit for all parameters except t 8 0.1 f 0.1 f clk out 10 pf v dd v dd outputs gnd gnd test circuit #2 test circuit for t 8 , output slew rate on -1h, -5 device 1 k ? 1 k ?
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